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Dual-delay-path ring oscillator with self-biased delay cells for clock generation

Dual-delay-path ring oscillator with self-biased delay cells for clock generation

Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra

ARTIGO

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Agradecimentos: The authors would like to thank the financial support provided by FINEP, CAPES, CNPq and Information Technology Center Renato Archer through the project CITAR (Radiation Hardened Integrated Circuits) for providing the resources and infrastructure for the accomplishment of this work

Abstract: This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply... Ver mais

FINANCIADORA DE ESTUDOS E PROJETOS - FINEP

COORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPES

CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQ

Aberto

Dual-delay-path ring oscillator with self-biased delay cells for clock generation

Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra

										

Dual-delay-path ring oscillator with self-biased delay cells for clock generation

Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra

    Fontes

    Circuits and Systems (Fonte avulsa)