Dual-delay-path ring oscillator with self-biased delay cells for clock generation
Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra
ARTIGO
Inglês
Agradecimentos: The authors would like to thank the financial support provided by FINEP, CAPES, CNPq and Information Technology Center Renato Archer through the project CITAR (Radiation Hardened Integrated Circuits) for providing the resources and infrastructure for the accomplishment of this work
Abstract: This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply...
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Abstract: This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V DD = 1.8 V, the resulting set of performance parameters include power consumption P DC = 4.68 mW and phase noise PN@ 1MHz = -107.8 dBc/Hz. From the trade-off involving P DC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool
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FINANCIADORA DE ESTUDOS E PROJETOS - FINEP
COORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPES
CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQ
Aberto
Dual-delay-path ring oscillator with self-biased delay cells for clock generation
Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra
Dual-delay-path ring oscillator with self-biased delay cells for clock generation
Agord de Matos Pinto Jr, Raphael Ronald Noal Souza, Mateus Biancarde Castro, Eduardo Rodrigues de Lima, Leandro Tiago Manêra
Fontes
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Circuits and Systems (Fonte avulsa) |